For several decades, integrated circuit and laser technologies have doubled in performance approximately every 18 months. These technologies have been used to support a rapidly-growing demand for global communications capacity. This demand is currently growing much faster than the underlying rate of improvement of the supporting technologies. As an example, communication traffic through the Internet has recently been doubling every nine months. The demand for additional communication bandwidth is severely stressing the capabilities of current electronic and optical technologies.
In particular, the Ethernet local area network standard has progressively increased in speed by factors of ten, starting at 10 megabit per second (Mb/s) in 1982. Proposals for a 10 gigabit/second (Gb/s) Ethernet standard were made in 1999. The most recently adopted Ethernet standard is for transmitting serial data at 1 Gb/s and uses a 8b/10b line code described by A. X. Widmer and P. A. Franaszek in A DC-Balanced, Partitioned-Block, 8b/10b Transmission Code, 27 IBM J. RES. AND DEV., (1983 September). In 8b/10b line code, each eight-bit input word is represented by a ten-bit code that is transmitted through the Ethernet medium. In exchange for this 25% overhead, 8b/10b coding provides DC balance, and a guaranteed transition density. The ten-bit code additionally has the ability to represent an assortment of control words used for signaling and framing.
The large overhead of 8b/10b coding imposes operational disadvantages when applied to 10 Gb/s transmissions. In U.S. patent application Ser. No. 09/522,782, the disclosure of which is incorporated herein by reference, one of the inventors of this disclosure (Walker) and others disclosed a 64b/66b encoder/66b coding scheme that provided most of the advantages of 8b/10b coding, but with a substantially smaller overhead.
FIG. 1 is a block diagram showing an example 10 of the 10 Gb/s Ethernet data communication system disclosed in the above-mentioned patent application. The data communication system receives a 4×8b/10b coded serial bitstream via the 4-lane XAUI bus 18 and outputs a 4×8b/10b coded serial bitstream via the 4-lane XAUI bus 19.
The data communication system 10 includes the transmitter 20 and the receiver 22. The transmitter 20 is composed of a serial arrangement of the 4×10b/8b decoder 32, the 64b/66b encoder 50, the scrambler 33, the frame assembler 34 and the multiplexer 35. The input of the 4×10b/8b decoder is connected to the XAUI bus 18. The output of the 4×10b/8b decoder is connected to the input of the 64b/66b encoder by the 37-conductor pseudo-XGMII bus 42.
The payload field output of the 64b/66b encoder 50 is connected to the input of the scrambler 33 by the payload field bus 43. The master transition output of the 64b/66b encoder is connected via the master transition bus MT to the master transition input of the frame assembler 34.
The output of the scrambler 33 is connected to the payload field input of the frame assembler 34 by the bus 44. The output of the frame assembler is connected to the input of the multiplexer 35 by the bus 45. The multiplexer generates a 10 Gb/s serial bitstream that is output to the Ethernet medium 40.
The receiver 22 is composed of a serial arrangement of the demultiplexer 36, the frame disassembler 37, the descrambler 38, the 66b/64b decoder 52 and the 4×8b/10b encoder 39.
The demultiplexer 36 receives a 10 Gb/s serial bitstream from the Ethernet medium 40. The output of the demultiplexer is connected to the input of the frame disassembler 37 by the bus 46.
The payload field output of the frame disassembler 37 is connected to the input of the descrambler 38 by the bus 47. The master transition output of the frame disassembler is connected to the master transition input of the 66b/64b decoder 52 by the bus MT.
The output of the descrambler 38 is connected to the payload field input of the 66b/64b decoder 52 by the bus 48.
The output of the 66b/64b decoder 52 is connected to the input of the 4×8b/10b encoder 39 by the 37-conductor pseudo-XGMII bus 49. The output of the 4×8b/10b encoder is connected to the XAUI bus 19.
The widths of the busses 43-48 shown in FIG. 1 are maximum parallel widths: serial/parallel techniques may be used to reduce the parallel widths of these busses substantially.
In the transmitter 20 of the data communication system 10, the 4×10b/8b decoder 32 is connected to the XAUI bus 18 to receive incoming serial 10-bit line code words at a bit rate of 4×3.125 Gb/s. The 4×10b/8b decoder decodes the 8b/10b coding of the 10-bit line code words to recover respective 8-bit words, and generates, a control word flag for each word that, when set, indicates that the word is a control word. The 4×10b/8b decoder sets of four of the 8-bit words and their respective control word flags to the 64b/66b encoder 50 via the pseudo-XGMII bus 42. In this disclosure, the term quad will be used to denote a set of four 8-bit words. The pseudo-XGMII bus is composed of 37 conductors of which thirty-two are allocated to the quads, four are allocated to the control word flags for the quads, and one is allocated to a clock signal.
The 64b/66b encoder 50 determines whether any of the eight control word flags belonging to two of the quads is set. When none of the control word flags is set, the quads are composed exclusively of information words, and the 64b/66b encoder generates a payload field composed of both of the quads. The 64b/66b encoder additionally generates the two-bit master transition with bits 0 and 1 in a first state. When at least one of the control word flags is set, the quads include at least one control word, and the 64b/66b encoder generates a payload field composed of a TYPE word and seven other words. The seven other words may be information words, compressed control words or both information words and compressed control words. The 64b/66b encoder additionally generates the two-bit master transition with bits 0 and 1 in a second state, opposite to the first state. The payload field structures will be described below with reference to FIGS. 2A-2C.
Regardless of the contents of the payload field and the sense of the master transition, the 64b/66b encoder 50 feeds the payload field to the scrambler 33 via its payload field output and the bus 43 and feeds the master transition, suitably pipelined, to the master transition input of the frame assembler 34.
The scrambler 33 scrambles the payload fields of the frames so that, when the frames are transmitted, the resulting bitstream is statistically DC balanced and additionally appears to be random. Scrambling the payload fields also enables the receiver to synchronize easily on the master transitions, which are not scrambled. In an embodiment of the data communication system 10, the scrambler scrambles the payload field using the polynomial x58+x39+x0. Alternative polynomials that can be used include x65+x47+x0, x58+x19+x0 and x65+x18+x0.
The frame assembler 34 receives the scrambled payload field from the scrambler 33 and the master transition from the 64b/66b encoder 50 and forms a 66-bit frame from the scrambled payload field and the master transition.
FIG. 2A shows the basic structure of the frame 70 generated from two quads. Each quad is composed of four 8-bit words. The frame is composed of the two-bit master transition field 71 followed by the 64-bit payload field 72. The master transition field 71 accommodates the two-bit master transition. As noted above, the payload field is scrambled by the scrambler 33 the frame 70 is formed.
Two different kinds of frame having the basic structure shown in FIG. 2A, but differing in the structure of their payload fields are generated. The structure of the payload field depends on whether or not the two quads are composed exclusively of information words. The structure of the payload field is indicated by the master transition stored in the master transition field. FIG. 2B shows the structure of the frame 73 generated when the two quads are composed exclusively of information words. In this, the master transition in the master transition field 71 is 01, and the payload field 72 is composed of the eight information words constituting the quads, i.e., 64 bits.
FIG. 2C shows the structure of the frame 76 generated when the quads include at least one control word. In this, the master transition in the master transition field 71 is 10, and the payload field 72 is composed of the eight-bit sub-field 77 and the 56-bit sub-field 78. The eight-bit sub-field is occupied by a TYPE word and the 56-bit sub-field is occupied by a compressed version of the quads. In particular, all information words included in the quads are included unchanged in the 56-bit sub-field. The 56-bit sub-field can accommodate up to seven information words, the maximum number of information words in two quads that include at least one control word. Moreover, the start-of-packet control word S and the end-of-packet control word T, if they appear in the quads, are discarded and are not transferred to the 56-bit sub-field. Instead, the value of the TYPE word indicates the presence and position of the control word S or the control word T. Finally, all remaining control words in the quads are compressed by re-coding them using fewer than eight bits and the re-coded control words are included in the 56-bit sub-field. In an embodiment, the remaining control words are re-coded using seven-bit codes chosen to have a mutual Hamming distance of four bits.
Returning now to FIG. 1, the multiplexer 35 receives the 66-bit frames from the frame assembler 34 and serializes them for transmission through the Ethernet medium 40 at a bit rate of 10 Gb/s.
In the receiver 22 of the data communication system 10, the demultiplexer 36 receives the serial data stream having a bit rate of 10 Gb/s from the Ethernet medium 40. The demultiplexer partitions the bitstream into 66-bit frames, and feeds the frames to the frame disassembler 37.
The frame disassembler 37 operates on each frame to separate the master transition from the scrambled payload field, and feeds the master transition, suitably pipelined, to the master transition input of the 66b/64b decoder 52. The frame disassembler also feeds the scrambled payload field to the descrambler 38.
The descrambler 38 descrambles the scrambled payload field using self-synchronizing descrambling complementary to the scrambling performed by the scrambler 33. The descrambler feeds the resulting recovered payload field to the payload field input of the 66b/64b decoder 52.
The 66b/64b decoder 52 decodes the recovered payload field in response to the corresponding master transition received from the frame disassembler 37. When the master transition is in its first state, the 66b/64b decoder simply outputs the eight words in the payload field as two consecutive quads. The 66b/64b additionally outputs a control word flag for each word in the quads. When the master transition is in its second state, the 66b/64b decoder reconstitutes the two quads from which the original frame was generated before outputting them together with a control word flag for each word in the quads. The 66b/64b decoder reconstitutes the two quads by reading the TYPE word and expanding any compressed control words in the field. Additionally, when the TYPE word indicates that either the start-of-packet control word S or the end-of-packet control word T was discarded by the 64b/66b encoder 50, the 66b/64b decoder additionally inserts a start-of-packet control word or an end-of-packet control word into the location in the quad indicated by the TYPE word.
The 66b/64b decoder 52 transfers the quads and their respective control word flags in parallel to the 4×8b/10b encoder 39 via the pseudo-XGMII bus 49.
The 4×8b/10b encoder 39 applies 8b/10b encoding to the quads received via the pseudo-XGMII bus 43, operating in response to the control word flag for each word constituting the quads. The 4×8b/10b encoder outputs the resulting 10-bit line code words via the XAUI bus 19.
It is customary to equip data communication systems with a self-test facility to enable the proper operation of the data communication system to be confirmed. Conventionally, the data communication system is tested by transmitting a test sequence composed of known sequence of random bit patterns through the data communication system and detecting errors at the receiver. The receiver may be co-located with the transmitter or may be remotely located.
FIG. 3 is a block diagram showing an example 60 of a data communication system incorporating a conventional self-test facility. The data communication system 60 is based on the communication system 10 shown in FIG. 1, and elements of the data communication system 60 that correspond to elements of the data communication system 10 are indicated by the same reference numerals and will not be described again here.
The data communication system 60 additionally includes the bit error rate tester 61, the selector 62 and the selector 63. Bit error rate testers are known in the art. The example of the bit error rate tester 61 shown includes the test sequence generator 64 and the error detector 65.
The selector 62 has two data inputs, a control input and a data output. One data input is connected to the output of the frame assembler 34. The other data input is connected to the output of the test sequence generator 64. The control input is connected to the control line 66. The data output is connected to the input of the multiplexer 35.
The selector 63 has a data input, a control input and two data outputs. The data input is connected to the output of the demultiplexer 36. The control input is connected to the control line 66. One data output is connected to the input of the frame disassembler 37. The other data output is connected to the input of the error detector 65.
When the self-test enable control signal STE on the control line 66 is not asserted, the selector 62 connects the output of frame assembler 34 to the input of the multiplexer 35, and the selector 63 connects the output of the multiplexer 36 to the input of the frame disassembler 37. In this state, the data communication system 60 operates as described above. When the STE control signal is asserted, the selector 62 connects the output of the test sequence generator 64 to the input of the multiplexer 35, and the selector 63 connects the output of the demultiplexer 36 to the input of the error detector 65. The error detector synchronizes automatically to the received test sequence output by the demultiplexer and generates an error signal each time the received test sequence includes an error. The error detector may count the number of errors occurring in a predetermined time or during receipt of a predetermined number of bits to generate a bit error rate.
A commonly-available test sequence generator that can be used as the test sequence generator 64 generates a test sequence composed of 231−1 (about 2.14 billion) bits. With a clock speed of 10 GHz, the test sequence has a cycle time of about 0.2 seconds, which is a convenient cycle time for most testing most types of data communication system. The test sequence generator outputs the test sequence in frames of 66 bits compatible with the input of the multiplexer 35.
However, a 231-bit test sequence has a maximum run length of 31 bits. A run length of 31 bits occurs in normal 64b/66b encoded bitstreams more often than once in 1010 bits. As a result, a 231-bit test sequence does not adequately test the error floor. A test sequence generator that generates a longer test sequence could be used, but at the expense of a substantially longer cycle time. The cycle time of a 258-bit test is about 333 days. This would make it difficult to repeat a part of the test sequence that caused the data communication system to fail.
Another disadvantage of the conventional test sequence generator is that the test sequence looks like an error to any receiver in the data communication system not in self-test mode. Some receivers may require significant time to recover from such an error state.
A further disadvantage is that the test sequence is introduced into the transmitter 20 downstream of the frame assembler 34, so that the test sequence does not test the synchronization acquisition capability of the demultiplexer 36.
Finally, the bit error rate tester 61 and the selectors 62 and 63 collectively add substantial circuit complexity to the data communication system 10.
Thus, what is needed is a self-test facility that employs a test sequence that has a run length long enough to test adequately the error floor of a high-quality data communication system.
What is also needed is a self-test facility that generates a test sequence having a short cycle time.
What is also needed is a self-test facility that generates a test sequence that does not appear as an error to receivers not in a self-test mode.
What is also needed is a self-test facility that generates a test sequence that additionally tests the synchronization ability of the demultiplexer.